Additionally, SEMATECH will host invitational pre-conference workshops on December 5. The workshops will focus on technical and manufacturing gaps affecting promising emerging memory technologies and III-V channels on silicon. Co-sponsored by Tokyo Electron and Aixtron, these workshops will feature experts from industry and academia debating the challenges and opportunities in these areas in a series of presentations and panel discussions.
During the IEDM conference, SEMATECH’s FEP experts will present research results at the following sessions:
- Session 6, Monday, Dec. 6 at 2 p.m.: Self-aligned III-V MOSFETS Heterointegrated on a 200 mm Si Substrate Using an Industry Standard Process Flow – demonstrates, for the first time, that III-V devices on silicon can be processed in a silicon pilot line with controlled contamination, uniformity and yield while demonstrating good device performance.
- Session 16, Tuesday, Dec. 7 at 9:05 a.m.: Prospect of Tunneling Green Transistor for 0.1V CMOS – investigates tunneling green transistors for low-voltage CMOS VLSI devices and circuits. Statistical data will show that sub-60mV/decade characteristics have been clearly demonstrated on 8 inch wafers. This work is an ongoing collaboration with Prof. Chenming Hu and his co-workers at University of California Berkeley. The results of the collaborative work will be presented by Professor Hu.
- Session 19, Tuesday, Dec. 7 at 4:25 p.m.: Metal Oxide RRAM Switching Mechanism Based on Conductive Filament Microscopic Properties – reports on critical conductive filament features controlling RRAM operations. The forming process is found to define the filament shape, which determines the temperature profile and, consequently, switching characteristics.
- Session 26, Wednesday, Dec. 8 at 9:55 a.m.: Contact Resistance Reduction to FinFET Source/Drain Using Dielectric Dipole Mitigated Schottky Barrier Height Tuning – shows, for the first time, a contact resistance reduction using dielectric dipole mitigated Schottky barrier height tuning on a FinFET source. This technique is very promising for emerging devices, alternative channel materials, and sub-22nm CMOSFETs, where the Schottky barrier height and resulting higher parasitic contact resistance are significant barriers for scaling.
- Session 34, Wednesday, Dec. 8 at 2 p.m.: Strained SiGe and Si FinFETs for High Performance Logic with SiGe/Si Stack on SOI – reports on a dual channel scheme for high mobility CMOS FinFETs.
source: http://edageek dot com/2010/11/08/nanowire-rram/
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